1. Field of the Invention
The present invention relates to a clock configuration for reducing an intra-chip clock delay variation in a clock synchronizing circuit of a semiconductor integrated circuit.
2. Description of the Related Art
In recent years, in the miniaturizing process of a semiconductor integrated circuit resulting from with a process shrink, an intra-chip clock delay variation due to the influence of the OCV (On-Chip-Variation) has caused serious problems such as the increase of man-hours in its manufacturing process, the deterioration of timing convergence in its characteristics, and area increase in its structure.
The OCV denotes an intra-chip clock delay variation generated in different clock paths in a clock synchronizing circuit which demands the adjustment of the clock delay. The OCV is induced by, for example, the following factors:                processing variation in the manufacturing process        inadequacy of the OPC (Optical-Proximity-Correction)        temperature variation in the chip at the time of an operation        variation of an IR-DROP value in each cell        variation of the number of cell layers        variation of a wiring shape        variation of a design factor which depends on an actual operation        other design margins        
The miniaturizing process requires such timing verification that the intra-chip clock delay variation due to the influence of the OCV is included in the design margins. In the case where the delay variation (an amount of variance) is 20%, for example, it is necessary to guarantee the operation frequency of 120 MHz in order to guarantee the operation frequency of 100 MHz.
In SRAM, ROM, dDRAM and the like (hereinafter, referred to as macros) which are custom-designed, it is conventionally necessary to set a hold time exceeding that of a flip-flop. Further, the area increase due to the OCV is eminent since these macros comprise a large number of input and output terminals.
It is a generally adopted configuration to provide a large number of macros to realize the reduction of chip costs and the improvement of performance. Therefore, the decline of productivity in the designing process, such as the increase of man-hours and the area increase, which is caused since the timing convergence between the flip-flops and the macros is deteriorated, is an issue that needs to be resolved.
FIG. 2 is an illustration of a conventional clock configuration. The clock configuration, in a semiconductor integrated circuit having a clock tree structure, comprises                a clock tree source cell 1001 which supplies clock signals;        a flip-flop 1004 and a macro 1005, which are circuits that require clock delay adjustment from the clock tree cell 1001;        a clock selecting circuit 1006 which selects a clock signal and outputs the selected clock signal to the macro 1005;        a first clock tree cell (ramified into a plurality of stages) 1002 which performs the clock delay adjustment in a poststage of the clock tree cell 1001;        a second clock tree cell 1003 which performs the clock delay adjustment in a prestage of the flip-flop 1004 and the macro 1005; and        a clock final ramification point 1007 at which a clock transmission path ramifies to the clock selecting circuit 1006 from the clock tree circuit.        
A clock signal outputted from the clock tree source cell 1001 is amplified by the first clock tree cell 1002 and the second clock tree cell 1003 each ramified into a plurality of stages at the clock final ramification point 1007, and transmitted to the flip-flop 1004. This clock signal is further amplified by the first clock tree cell 1002 and the second clock tree cell 1003 each ramified into the plurality of stages after passing through the clock selecting circuit 1006 via the clock final ramification point 1007, and transmitted to the macro 1005. Therefore, the clock path from the clock tree source cell 1001 to the flip-flop 1004 and the clock path from the clock tree source cell 1001 to the macro 1005 are subjected to the clock delay adjustment by the first clock tree cell 1002 and the second clock tree cell 1003.
Accordingly, the clock final ramification point 1007 and the clock selecting circuit 1006 are placed in the prestage of the clock path in comparison to the first clock tree cell 1002 ramified into the plurality of stages, and the clock selecting circuit 1006 is placed in proximity to the clock tree source cell 1001. Therefore, the length of the clock path is different between the two after the clock final ramification point 1007. As a result, the intra-chip delay variation due to the OCV is increased, and the man-hour increase and the area increase caused by the deterioration of the timing convergence occur.
In order to solve the problem, a design method recited in Japanese Patent No. 3178371 was proposed. The design method centered around a group of flip-flops which receive clock signals generated by a gating clock circuit capable of reducing power consumption in a clock line, and a delay time difference (skew) generated in the group of flip-flops was lessened.
More specifically, the processes performed by the design method are as follows.                In the gating clock circuit having a clock tree structure in which a route buffer, buffers in a plurality of stages which are sequentially ramified from the route buffer, and a final stage multi-input gate (NOR gate) are combined, these components are connected after all of cells are placed.        After the flip-flops connected to the clock line are clustered on a function-by-function basis, and the flip-flops placed in proximity are further clustered relative to each other.        
As a result, loads driven by the respective buffers and the multi-input gate can be constant, which lessens the skew.
In the conventional method described above, since the final multi-input gate is provided at the center of gravity coordinate of the flip-flops driven by the respective buffers, a complicated placement clustering process is required. Further, it is not possible for the method to flexibly deal with a macro subject to placement restrictions different to those of the flip-flop and a complicated clock selecting circuit configured in a manner different to the gating circuit.